In most computer systems, there exists a mechanism to interrupt the host processor to handle high priority events. Priority interrupts are often used to signal to the host processor the completion of I/O command execution, the occurrence of asynchronous events, or the occurrence of severe errors. A priority interrupt causes a lower priority program which is executing in the host processor to be temporarily halted, and it allows the execution of a program to handle the priority interrupt. This program is called an interrupt handler. Priority interrupts are used when fast response to asynchronous events is desired.
In many computer systems, there is a relatively large amount of overhead in processing a priority interrupt. For example, pointers and register must often be saved when the interrupt handler is started and then restored for the program that was interrupted. It is possible for the overhead processing to exceed that amount of processing required to process the data from the interrupt. When a large number of interrupts occur over a short period of time, the overhead can become very significant, and can result in relatively long delays in the servicing of priority interrupts. Long delays can significantly reduce overall system performances.
According to the present invention, the number of priority interrupts to the host system during periods of high interrupt activity is reduced, which increases the overall system performance. This is accomplished by allowing one or more logical interrupts to be presented to the host system through one priority interrupt from a subsystem. A logical interrupt describes an event that normally results in a priority interrupt. However, a logical interrupt may or may not cause a priority interrupt, depending upon whether another priority interrupt is currently being processed. This invention allows the interrupt handler in the host system to detect the occurrence of logical interrupts without actually receiving a priority interrupt. By detecting the presence of logical interrupts (and resetting them), priority interrupts can be reduced, interrupt latency can be reduced, and overall system performance can be improved.